HPPC 2011

HPPC - Workshop on Hardware-support for parallel program correctness

Held in conjunction with MICRO-44
Porto Alegre, Brazil -- December 4^th, 2011

About HPPC

The proliferation of multi-core processors both in desktop as well as in the mobile computing environments is leading to a wider adoption of shared-memory and message passing parallel programming. These are standard methods to exploit the full performance potential available on those chips. While the performance benefits are undeniable, correct parallel programming is very hard to achieve because of the subtle interactions among many threads of execution. These lead to concurrency run-time errors which are challenging to detect and repair. To address correctness issues, developers and end users need tools to help preventing, detecting and correcting defects in parallel programs.

Software tools for static and dynamic concurrency violation detection, parallel programming testing, bug reproduction and bug root causing have been the focus of much recent research. While these tools are functionally effective, they often incur high runtime overhead, which severely limits their applicability in many cases. Consequently, the natural direction for future multi-core processors is to add hardware features to support and facilitate the development of correctness tools and techniques for parallel programs.

The organizers of HPPC invite all the researchers in this area to submit their work and discuss future hardware enhancements necessary to advance the state-of-the art in validation, testing and correctness of parallel programs.

Submission Topics

Topics of interest include, but are not limited to:

Architecturally visible hardware counters for profiling and debugging (e.g. additional performance counters, etc) parallel programs
CPU+GPU correctness and debugging features
Hardware support for runtime analysis tools (e.g. data race detections, atomicity violations, etc)
Hardware support for runtime concurrency issues detection
Hardware support for hybrid (static + dynamic) analysis for correctness
Hardware support for software testing (e.g. efficient mechanisms to measure test coverage metrics) and validation
Mechanisms for homogeneous and heterogeneous multi-core tracing/profiling
Record & replay solutions
Systems-on-chip (SOC) correctness, tracing and debugging features

Important Dates

~~September 16^th~~ October 7^th 2011 (11:59pm PST): Paper deadline
~~October 28^th~~ November 9^th 2011: Notification of acceptance
December 4^th 2011: Workshop date

Submissions

Please, submit your paper using EasyChair at https://www.easychair.org/conferences/?conf=hppc11.

Workshop Organizers

Cristiano Pereira - Intel
Gilles Pokam - Intel

Program Committee

Cristiano Pereira - Intel
Edson Borin - U. of Campinas, Brazil
Gilles Pokam - Intel
Josep Torrellas - U. of Illinois, Urbana-Champaign
Luis Ceze - U. of Washington
Mauricio Breternitz - AMD
Pablo Montesinos - Qualcomm
Rajiv Gupta, U. of California, Riverside
Satish Narayanasamy - U. of Michigan, Ann Arbor
Shan Lu - U. of Wisconsin, Madison